Exemplary embodiments of the present invention relate to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a semiconductor device with buried bit lines.
As the degree of integration for Dynamic Random Access Memory (DRAM) devices increases, two-dimensional (2D) structures are reaching limits. Thus, three-dimensional (3D) DRAMs with vertical gates (VG), which are referred to hereinafter as VG DRAM, are being developed.
A 3D DRAM having a vertical gate structure may include active regions, each of which is formed of a body and a pillar formed over the body, buried bit lines BBL, and vertical gates VG. The bodies of adjacent active regions are separated from each other by a trench and the buried bit lines BBL are formed within the trenches. Each buried bit line BBL is electrically connected with a sidewall of each active region. Each vertical gate VG is formed on one sidewall of a pillar over a buried bit line BBL, and a source and a drain are formed within the pillar. The vertical gate VG is used for formation of a vertical channel between the source and the drain.
In order to drive a cell in a buried bit line BBL, a One-Side-Contact (OSC) process may be used. The one-side contact process may be also referred to as a Single-Side-Contact (SSC). The one-side contact process is a process for forming a contact in an active region while insulating the active region from adjacent active regions.
Since bit lines have a buried structure in the three-dimensional DRAM having a vertical gate structure, the area of the buried bit lines BBL is limited. Therefore, a metal layer may be used to form the buried bit lines BBL with a low bit line resistance. In order to fill a metal layer in deep trenches without void, a Chemical Vapor Deposition (CVD) process or an Atomic Layer Deposition (ALD) process may be used.
Buried bit lines BBL may be formed of a titanium nitride (TiN) layer and a tungsten (W) layer. The titanium nitride (TiN) layer and the tungsten (W) layer are deposited through the CVD process.
Here, when the line width of the buried bit lines BBL is decreased, drastic resistance increase may occur because the area occupied by tungsten (W) in the buried bit lines BBL is decreased while the thickness of the titanium nitride (TiN) layer remains the same.
Since the CVD process results in rough surfaces of the tungsten layer, void and seam may be created.
When a subsequent etch-back process is performed to acquire a desired bit line height, the buried bit lines BBL may be cut undesirably or punctured all the way through to the lower substrate and thus defective semiconductor device products may result.